发明名称 System and method for processing a plurality of branch instructions by a plurality of storage devices and pipeline units
摘要 An instruction pipeline in a microprocessor is provided. The instruction pipeline includes a plurality of pipeline units, each of the pipeline units processing a plurality of instructions including branch instructions. The instruction pipeline further includes a plurality of storage device which store a respective branch information data. Each of the storage devices are associated with at least one of pipeline units. Each respective branch information data is determined as a function of at least one of the branch instructions processed. Two of the pipeline units include branch prediction circuitry for predicting branch direction as a function of the stored branch information data.
申请公布号 US6055630(A) 申请公布日期 2000.04.25
申请号 US19980063205 申请日期 1998.04.20
申请人 INTEL CORPORATION 发明人 D'SA, REYNOLD V.;KYKER, ALAN B.;SHEAFFER, GAD S.;ESPINOSA, GUSTAVO P.;KALAFATIS, STAVROS;HEBDA, REBECCA E.
分类号 G06F9/38;(IPC1-7):G06F13/14 主分类号 G06F9/38
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