MEMORY ADDRESS COUNTER HAVING AN END-OF-COUNT DETECTOR

摘要

PURPOSE: A memory address counter is provided to reduce a die area and a power consumption. CONSTITUTION: An address counter stage is designed with a first latch circuit which is coupled to receive a start address bit and store the received address bit. A second latch circuit is coupled to receive a present address bit to then store the received address bit. A third latch circuit is coupled to receive a next address bit to then store the received address bit. A switching circuit is coupled between the second and third latch circuits. The switching circuit is configured to couple an output of the third latch circuit to an input terminal of the second latch circuit in response to a clock signal. An EXOR circuit is coupled to receive the start address bit and the next address bit.