| 摘要 |
PURPOSE: A floating gate memory cell for preventing current leakage is provided to improve data retention, to decrease fail rate, to minimize and to selectively grow a salicide in a part of region of memory IC without decreasing the reliance of a memory cell or a salicide transistor. CONSTITUTION: An integrated circuit comprises: a floating gate(69) formed on a gate oxide (49,59) on a substrate(48) of a first conductive type and having a length determined by a first wall pair restricting side of the floating gate(69); a polymerized oxide(68) formed on the floating gate(69); a control gate(43,53,63) formed on the polymerized oxide(68) and having a length determined by a second wall pair restricting side of the control gate; source regions(45a,45b,55a,55b,65a,65b) of a second conductive type located closely to the first wall among the second wall pair of the control gate; drain regions(47a,47b,57a,57b,67a,67b) of a second conductive type located closely to the second wall faced to the first wall among the second wall pair of the control gate(43,53,63); an oxide regrowth layer(73) covering the first wall pair of the floating gate(69) and having the sufficient thickness to prevent charge tunneling through the oxide regrowth, and additionally having a characteristic sensitive to a predetermined etchant; and an insulation coating layer(79) formed on one of the first wall pair and having tolerance to the etchant. |
