DELAY STAGE HAVING STEEP EDGE

摘要

PURPOSE: A delay stage having steep edge is provided to structure a time delay relay with relative few number of parts CONSTITUTION: A delay stage having steep edge comprises first inverters(M1,M2), second inverters (M3,M4), a p-channel transistor(M5) and n-channel transistor(M6). The inverters(M1-4) are serially connected each other. The inputs of the first inverters correspond to the input(E) of the delay stage and the outputs of the second inverters correspond to the output(D) of the delay stage. The p-channel transistor(M5) connected as a capacitor is connected between a gate of the p-channel MOS transistor of the second inverter and the output of the delay stage and the n-channel transistor(M6) is connected between a gate of n-channel transistor of the second inverter and the output of the delay stage.