发明名称
摘要 PURPOSE:To set the constitution of a processing system to be simple and without malfunction by dividing a carrier frequency as a frequency-dividing number which sets one of the least common multiples of the carrier frequency and a clock frequency to be a period and reproducing the switching clock of a carrier by means of a multiphase modulation waveform. CONSTITUTION:A frequency divider 3 sets the least common multiple of the carrier frequency f1 and the clock frequency, '9' when the carrier frequency is set to the 1800Hz and the clock switching frequency to be 1600Hz, for example, and makes it the frequency-dividing number. A reset command is given to a frequency divider 4 from a first detector 5 detecting a fall in the output frequency of the frequency divider 3 and a reference oscillation frequency fR is frequency-divided. Thus, a frequency f2 in which the carrier by multiphase PSK modulation is synchronized with the clock frequency is taken out and a switching frequency is generated by taking out the reference frequency of the clock from the demodulator and frequency-dividing it. Then, frequency-division is resumed by adjusting it to the timing of a reset pulse and therefore, a reproduced clock frequency which has been synchronized with a switching timing can be obtained.
申请公布号 JP3037339(B2) 申请公布日期 2000.04.24
申请号 JP19890106456 申请日期 1989.04.25
申请人 发明人
分类号 H04L27/22;H04L7/00;H04L7/027 主分类号 H04L27/22
代理机构 代理人
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