| 摘要 |
PROBLEM TO BE SOLVED: To simultaneously manufacture a vertical bipolar transistor and a junction field-effect transistor without production of non-etched parts, while preventing production of deficiencies in characteristics. SOLUTION: A gate region 17 is provided in a channel area 16 between a source region 14 and a drain region 15. The source area 14, the drain region 15 and the gate region 17 are formed by impurities diffusion from a source drawing layer 21 of polycrystalline silicon containing impurities, a drain drawing layer 23 and a gate drawing layer 18 as diffusion sources through an opening 20a of an insulating film 20. The source drawing layer 21 and the drain drawing layer 23 are formed by forming a polycrystalline silicon layer containing impurities, in such a way that it covers the whole ring-shaped opening 20a, forming a ring-shaped opening in the polycrystalline silicon layer and separating the polycrystalline silicon layer. In this case, the opening is formed inside the opening 20a formed in the insulating film 20.
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