HARD/SOFT INTERLOCK SIMULATION METHOD

摘要

PROBLEM TO BE SOLVED: To provide a hard simulation method based on an efficiently executable command instruction while facilitating the description of a test pattern. SOLUTION: A soft simulation part 300 capable of executing the simulation of a program and a hard simulation part 200 capable of executing the simulation of a VHDL described circuit 210 are connected. By packaging a program for performing command executing in the soft simulation part 300 as a command part 100, the simulation can be executed by the command.