发明名称 INFORMATION PROCESSOR HAVING MULTIPLEX ADDRESS CONVERTING MECHANISM
摘要 PROBLEM TO BE SOLVED: To realize an address conversion based on respective architectures in the case of sharing a main storage by plural processors having respectively different instruction architectures through a storage control. SOLUTION: Respective processors (a), (b) are provided with respectively different instruction architectures and each of main storages 210-213 is provided with a DAT processor, a DAT controlling storage and a software TLB. When a main storage access request is outputted from the processor (a) e.g. a TLBa is retrieved, and when there is no logical address, a DATa is started, an address conversion request with an IP number, a logical address and architecture ID is transferred to a DAT processor through a system control part SC. The DAT processor retrieves a software TLB corresponding to the conversion request, and when a logical address exists, registers a conversion result in the software TLB, registers the result also in the TLBa and stops the operation of the DATa. When no logical address exists a corresponding DAT program stored in the DAT control storage is started and a conversion result is registered in the software TLB.
申请公布号 JP2000112821(A) 申请公布日期 2000.04.21
申请号 JP19980300423 申请日期 1998.10.07
申请人 HITACHI LTD 发明人 ONODERA OSAMU
分类号 G06F12/08;G06F12/10;G06F15/167;(IPC1-7):G06F12/10 主分类号 G06F12/08
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