| 摘要 |
PROBLEM TO BE SOLVED: To suppress the inversion of invalid bits of high orders, reduce a consumption current and also suppress power source noise by changing the word length of a computing element in accordance with the level of an input digital signal. SOLUTION: An input level deciding means 12 decides the level of a binary digital signal of two complement representations inputted from a digital signal inputting terminal 11. The operation results of a variable word length operating means 14 in which an operation word length can be changed by a decision output signal 13, is outputted from an outputting terminal 15. The digital signal is represented in two complements, for instance, a numerical range represented by eight bits is between +127 and -128, when the decision between +7 and -8 is performed, the decision can be performed if a coincidence detection circuit whose five bits of high orders are zero or one is provided and when all the bits are zero ore one, zero is outputted. The means 14 operates with 4-bit operation word length when the decision output 13 of an input level decision circuit is zero, and operates with 8-bit operation word length when the output 13 of the input level decision circuit is one. |
