| 摘要 |
PROBLEM TO BE SOLVED: To provide a sequential trigger discrimination circuit that can detect a sequence of an expected trigger cause without increasing the circuit scale and the scale of the software. SOLUTION: A trigger cause latch circuit 12 latches trigger causes ITRG0-7. A fixed value x'00' is given at first to a high-order address of a memory 13 and trigger causes ITRG0-7 are given to the low-order addresses. Contents of the address corresponding to each trial order number are stored in the high- order address to be given to a succeeding train order number and a default denoting end of sequence is set as a last trigger cause. An output data latch circuit 14 latches an output of the memory 13 to a high-order address of the succeeding trial order number. A channel selection circuit 15 selects a channel where a trigger signal is generated based on the high-order address and a sequence end detection circuit 16 detects the end of sequence. An output circuit 17 generates a sequence end trigger of the channel that is selected at the end of sequence among sequence end triggers TRG0-7.
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