| 摘要 |
<p>PROBLEM TO BE SOLVED: To effectively display the original performance of a product and to make it possible to drive an integrated circuit at high clock frequency by judging and fixing the frequency of a clock signal by using a judging path having shot set-up time or hold time. SOLUTION: A clock from an oscillator 2 is adjusted by a clock frequency adjuster 3 and inputted to an IC chip 1 as a reference clock signal. When the clock signal is sequentially shifted from the low frequency side to the high frequency side, both judging paths 11, 12 are normally driven at first, but the path 12 is not normally driven at a certain frequency f2. When the frequency is increased, both the paths 11, 12 are not normally driven at a certain frequency f1. A lock signal is outputted from a PLL controller 4 before arrival at the frequency f1, so that the frequency is fixed on f2<=f<=f1 at the time. Since the set-up time or the like of the path 11 is set up shorter than a critical path 7, the original performance of the product can be effectively displayed.</p> |
