| 摘要 |
PROBLEM TO BE SOLVED: To perform fast data transfer at low cost by receiving synchronous data and image data, which are alternately transmitted and stopping phase matching of a reception clock using the synchronous data, while receiving the image data. SOLUTION: Serial data 110 transferred from a data transmitter are inputted to a phase comparator 11, which constitutes a data modulation part 21 and a PLL. The phase comparator 11 compares a phase of the serial data 110 with a phase of a frequency division clock signal 150 which is obtained by frequency- halving a reception clock signal 140 outputted from a voltage-controlled oscillator(VCO) 13, outputs a phase difference signal 120 and inputs it to an LPF 12. An output of the LPF 12 becomes a signal for controlling the frequency of the output signal of the VCO 13. Here, while the data demodulation part 21 receives image data, phase matching by the phase comparator 11 constituting the PLL is stopped. Thus, it is possible to reduce the number of transmission devices.
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