| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a high-speed arithmetic unit capable of simultaneously executing the storage of input data and the reading of a stored operation result during the arithmetic operation of an operation part and accessing devices in a wide range with a simple constitution by individually applying the storage of input data, the storage of an operation result of input data and the reading of the stored operation result at least to three shared memories or multi-port memories. SOLUTION: One of shared memories 1-1 to 1-3 cyclicly executes a 1st stage for storing input data by connecting the shared memory itself to an input control part 4, a 2nd stage for performing an arithmetic operation and storing the operation result by connecting itself to an operation part 3 and a 3rd stage for outputting the operation result by connecting itself to an output control part 5. Since the other shared memories cyclicly execute the 1st to 3rd stages temporally shifted states, three shared memories are driven on respectively different stages at the same time. The operation part 3 instructs the cyclic connection switching to the bus connection control part 2.</p> |
