| 摘要 |
PROBLEM TO BE SOLVED: To provide a clock generation circuit which does not have to compensate frequency deviation in the process of the leading-in of a VCO. SOLUTION: A selection circuit 3 is provided between a 1st VCO 1 and a 4th VCO 4, and a switching signal generation circuit 2 is further provided which detects change of the state of an input frequency f0 and outputs a switching signal to the selection circuit only for a fixed time when detecting the change. A frequency f1 is supplied to the 2nd VCO in a state with no change, and the input frequency f0 is supplied to the 2nd VCO only for a fixed time when detecting the change. |
