| 摘要 |
<p>PROBLEM TO BE SOLVED: To erase a load charge voltage with a column format memory matrix by comprising a PMOS type first transistor having a conductive terminal in which one is connected to a main word line and the other is connected to a local word line, a NMOS type second transistor having a conductive terminal in which one is connected to a local word line and the other is connected to the reference voltage. SOLUTION: A storage device 1 is connected in the upstream of each local row LWL of a memory matrix within each sector of a non-volatile memory matrix. The storage device 1 includes the PMOS type transistor M1 connected to the conductive terminal between the main word line MWL and local word line LWL and the NMOS type transistor M3 connected to the conductive terminal between the local word line LWL and reference voltage GND. The gate terminals of all transistor M3 of the storage device 1 are all connected together to receive a voltage signal. Thereby, row decoding of the hierarchical structure may be realized.</p> |
