A simplified process for defining the tunnel area in semiconductor non-volatile non-aligned memory cells

摘要

The invention relates to a simplified non-DPCC process for the definition of the tunnel area in non-volatile memory cells with semi-conductor floating gate, which are non-aligned and incorporated in a matrix of cells with associated control circuitry, to each cell a selection transistor being associated, the process comprising at least the following phases: growth or deposition of a dielectric layer of gate of the sensing transistor and of the cells; tunnel mask for defining the area of tunnel; cleaning etching of the dielectric layer of gate in the area of tunnel up to the surface of the semi-conductor; growth of tunnel oxide; Advantageously, the tunnel mask is extended above the region occupied by the selection transistor. <IMAGE>