Synchronous semiconductor device allowing reduction in chip area by sharing delay circuit

摘要

A control signal generating circuit in a synchronous semiconductor memory device outputs timing signals for controlling activation of a word line and activation of sense amplifier, by delaying an external control signal by prescribed time periods. A bank control signal generating circuit provided for each bank holds activation of the timing signal from the control signal generating circuit, and outputs a signal for controlling timing of activation of the word line and timing of activation of the sense amplifier of the corresponding bank.