Method and apparatus for all digital holdover circuit

摘要

An all-digital phase-locked loop (ADPLL) device includes a primary ADPLL circuit and a controller which allow an in-phase output signal to be generated even when the incoming reference signal is lost. The primary ADPLL loop includes a phase detector, a digital loop filter, a first digital control oscillator (DCO) for generating a loop signal which is phase-locked to a received reference signal, and a frequency divider. The controller generates control signals to be used by a secondary DCO or the first DCO to generate a synchronized system output signal. The controller includes an accumulator which accumulates the number of phase-hopping events performed by the first DCO for a certain time period, a first-in-first-out (FIFO) buffer which stores a number of consecutive phase-hopping samples from the accumulator, and a calculator for determining an average of the consecutive values stored in the FIFO buffer. The control signals generated by the controller may be used by the secondary DCO to achieve a synchronized system output signal during both normal and holdover operating modes, or may be used by a single DCO only during the holdover mode.