| 摘要 |
PURPOSE: A digital DLL of an SDRAM is provided which is converted into a fast tracking mode when the DLL exits a power-down mode or self-refresh mode to be re-locked before the next effective instruction word is input to the DLL. CONSTITUTION: A digital DLL of an SDRAM includes a buffer(10) for receiving and buffering an external clock, a phase detector(14) for comparing the phase of a reference clock of the buffer with the phase of an inner clock, and a domain detector(13) for receiving the phase signal of the phase detector and the reference clock and comparing the domains of the signals. The DLL further has an initial match detector(12) for receiving the phase signal, the detection signal of the domain detector and the reference clock to lock the LDD according to the signals, a DLL counter(15) and clock divider(16) for receiving the phase signal to correct the phase of a DLL clock according to the reference clock, and a clock generator(17) for receiving a clock having a predetermined frequency according to the locking signal of the initial match detector to generate a clock based on the reference clock. The DLL also has a shift-left section(18) for receiving a negative signal from the DLL counter and clock divider to generate a shift-left signal, a shift-right section(19) for receiving a positive signal from the DLL counter and clock divider to generate a shift-right signal, and a clock delay(20) for receiving the output signal of the shift-left section or shift-right section to delay the clock by the time corresponding to the output signal. The DLL further includes a delay(11) for determining the phase of the inner clock feedback to the phase detector, a falling edge detector(31) for receiving a power down flag signal or self-refresh flag signal to detect the falling edge of the signal, and an SR latch(32) for setting or resetting fast tracking mode by the detection signal of the falling edge detector.
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