| 摘要 |
PURPOSE: A driving circuit for dividing data through of memory capacity is provided to achieve easy configuration of one chip by using a small capacity of memory and cost saving by using reduced gate count. CONSTITUTION: A first to a fourth memory block(110-140) sequentially store a half of every data (D1,D2,D3,D4...) outputted from a multiplicity of ICs, synchronizing with write enable signals(WE1-1,WE1-2,WE2-1,WE2-2). A first delay memory block(150) stores the data of the first memory block(110), synchronizing with a first read enable signal(OE1) inputted to a write enable terminal. A second delay memory block(160) stores the data of the second memory block(120), synchronizing with a second read enable signal(OE2). A first multiplexor(210) receives the inputs of the data (D1-1',D1-2') outputted from the first and the second memory block. A second multiplexor(220) receives the inputs of the data of the third and the fourth memory block.
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