| 摘要 |
PURPOSE: A high-speed D flip flop is provided to operate at a rising edge and at a falling edge with less components. CONSTITUTION: A first latch receives a clock signal and a first data signal, and generates a first output signal having an inverted version of a logic value of a data signal which is inputted in a low level period of the clock signal. The first latch operates according to a logic value of the first data signal in a high level period of the clock signal, and generates the first output signal of a low level when the first data signal is at a high level. A second latch receives the first output signal as a second data signal, and generates a second output signal in a low level period of the clock signal. The second latch operates according to a logic value of the second data signal in a low level period of the clock signal, and generates the second output signal of a low level when the second data signal is at a high level. A third latch receives the second output signal as a third data signal, and generates a third output signal having an inverted version of a logic value of the third data signal which is inputted in a high level period of the clock signal. The third latch operates according to a logic value of the third data signal in a low level period of the clock signal, and generates the third output signal of a low level when the second data signal is at a high level.
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