| 摘要 |
PURPOSE: A clock jitter mitigating apparatus is provided to minimize a clock jitter by predicting a jitter value and an affect according to the jitter. CONSTITUTION: A clock jitter mitigating apparatus comprises a counter(200), a memory(210), a part(220) and a protection block(230). The counter(200) is driven by a local clock. The memory(210) stores a first differential value between a synchronous residual time stamp(SRTS) value detected by a detection part and a synchronous residual time stamp generated at a local, and stores a second differential value between the stamp values when a count value of the counter reaches a predetermined value. The part(220) obtains a third differential value between the first and second differential values. The protection part(230) maintains a previous digital phase synchronous loop value or varies TSDO value by a constant value when the third differential value has a specific value. The protection part recognizes as an error when the third differential value has a different value except the specific value, to maintain a previous state.
|
