| 摘要 |
PURPOSE: A full adder is provided to calculate and output a carry signal as rapidly as a delay velocity in one exclusive-OR gate. CONSTITUTION: An exclusive-OR gate(XOR1) receives and exclusively ORs input signals(A)(B). An exclusive-OR gate(XOR2) receives and exclusively ORs the output of the exclusive-OR gate(XOR1) and an input signal(C) and outputs an adding signal(SUM). A carry signal calculating unit(100) receives the input signals(A),(B),(C) and outputs a carry signal(CA). PMOS transistors(PM1)(PM2) are connected to a power source voltage(VCC) in parallel, and each drain is commonly connected, and receives the input signals(B)(A) to each gate. A PMOS transistor(PM3) and an NMOS transistors(NM3) drain connecting dot thereof are connected to the PMOS transistors(PM1)(PM2) in serial, and receives the input signal(C) in each gate. NMOS transistors(NM1)(NM2) each drain thereof is connected to the source of the NMOS transistors(NM3) in parallel, and each source is connected to a VSS, and receives the input signals(B)(A). In addition, PMOS transistors(PM4)(PM5) and NMOS transistors(NM4)(PM5) are provided. An inverter(INV1) is commonly connected to the drain connection dot of the PMOS transistor(PM3), the NMOS transistor(NM3) and the drain connection dot of the PMOS transistor(PM5), the NMOS transistor(NM4). The inverter(INV1) receives and reverses an output of the common connection dot and outputs a carry signal.
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