SYNCHRONOUS SEMICONDUCTOR MEMORY DEVICE HAVING WAVE PIPELINING CONTROL SCHEME AND DATA OUTPUT METHOD

摘要

PURPOSE: A synchronous DRAM(Dynamic Random Access Memory) and a method for outputting data for the same are provided to prevent mis-operation of outputting data by delaying the first clock pulse signal. CONSTITUTION: The DRAM successively outputs plural data in a period of a read mode. The DRAM includes a register(201) and a controller(203). According to a control signal(NDLO) from the controller(203), the register(201) stores an output data(DIOB) from a memory cell. The controller(203) generates the control signal(NDLO) according to the first and second external clock signals(CLK0,CLK1). Level transition of the control signal(NDLO) occurs according to the last transition one of a subsidiary signal(XAD) and a preliminary signal(XPRE). Level transition of the subsidiary signal(XAD) occurs when the first external clock signal(CLK0) rises up. Level transition of the preliminary signal(XPRE) occurs when the second external clock signal(CLK1) rises up. Thereby, mis-operation of outputting data can be prevented.