SYNCHRONOUS SEMICONDUCTOR MEMORY DEVICE

摘要

PURPOSE: A synchronous semiconductor memory device is provided to have a clock signal generating circuit having a noise immunity. CONSTITUTION: An integrated circuit comprises a reset circuit(206) and a dynamic inversion circuit(204). The reset circuit(206) is connected to an input node for receiving an input signal, and generates a reset signal of a pulse form after the input signal is activated and a time elapses. The dynamic inversion circuit(204) is connected to the input node, and inverts the input signal and to outputs the inverted input into signal into an output node. The dynamic inversion circuit(204) is inactivated and is reset according to the reset signal.