| 摘要 |
PURPOSE: An external bus interface is provided to reduce an overhead of a memory controller and to perform a byte and halfword operations of a direct memory access(DMA). CONSTITUTION: The first and second multiplexers(302, 303) multiplex and output the data inputted from a data input/output pad by a control signal outputted from a memory controller. The first multiplexer unit receives data outputted from the first and second multiplexers(302, 303) and multiplexes and outputs again the data. The fourth and fifth multiplexers(304, 305) receive data outputted from the first multiplexer unit and multiplexes and outputs the data by a control signal corresponded to a position of a bus. The sixth multiplexer(306) receives data outputted from the fourth and fifth multiplexers(304, 305) and multiplexes and outputs again the data.
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