SHALLOW TRENCH ISOLATION METHOD FOR SEMICONDUCTOR USING CHEMICAL-MECHANICAL POLISHING

摘要

PURPOSE: A method for forming a shallow trench device isolation structure is provided to exactly detect an etch stop point(ESP) of a polishing process by transferring a supply power applied to a wafer chuck to a slurry solution via a wafer and allowing variation in current detected in the slurry solution to have a large value depending on the type of material polished on the surface of the wafer. CONSTITUTION: A thermal oxide film is deposited on a silicon substrate. A given conductive layer and a nitride film are sequentially deposited on the thermal oxide film. After forming a resist pattern on the nitride film, the nitride film is etched using the resist pattern as a mask. After the resist pattern is stripped, the conductive layer, the thermal oxide film and the silicon substrate are sequentially etched using the nitride film pattern as a mask, thus forming a trench. After selectively etching the nitride film pattern, a given insulating layer is deposited on the resulting surface and is then polished by chemical-mechanical polishing process. The conductive layer remaining in the wafer is selectively etched and the insulating layer is experienced by dry etch process so that a shallow trench isolation(STI) structure in which the insulating layer(250b) is flat filled in the trench formed at the silicon substrate(210a).