ESD PROTECTION CIRCUIT WITH PAD CAPACITANCE-COUPLED PARASITIC TRANSISTOR CLAMP

摘要

An ESD protection circuit (150) has first (101) and second (102) circuit terminals, and a lateral bipolar junction transistor (Q), which has a collector terminal coupled to the first circuit terminal and an emitter terminal coupled to the second circuit terminal. A capacitor (C) is coupled between the first circuit terminal and base terminals of the bipolar junction transistor, wherein the base terminals are close to and in-line with the base region. The capacitor has a low impedance to ESD events applied to the first circuit terminal so that ESD events cause the bipolar junction transistor to turn on in forward conductance mode to conduct ESD current from said ESD event without breakdown of the collector-base junction of the transistor.