| 摘要 |
The frequency divider has several signal transmission units which are series connected into a ring, such that the output of each unit is coupled to the input of the following unit. The output of the last unit is coupled to the input of the first unit. The signal transmission in at least one unit of the ring is influenced by the frequency of the input clock such that parallel to the output (A) of output stage (31), and controlled by previously transmitted signal, is linked the output of an extra control unit (32), whose output current (i2) is changed by the input clock (CLK).
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