PACKET BUFFER DEVICE

摘要

A packet buffer device that efficiently uses a buffer and a time, both used for packet assembly, in a packet header analysis and addition processing. The packet buffer device receives VC-multiplexed ATM cells, assembles the cells into cell-based packets for each VC, and outputs them on a packet basis. As an example, the packet buffer device has a sequence controller which performs a control that involves: assembling a packet by storing the cells of the packet, from the header cell to the end cell, into a packet buffer memory, which has a plurality of cell buffers for storing received packets on a cell-basis; detecting the completion of writing of a new header cell; and connecting a packet-under-assembly queue consisting of under-assembly pointers to an output waiting queue.