| 摘要 |
<p>PROBLEM TO BE SOLVED: To reduce the burden on software processing when performing the data transmission of a large capacity. SOLUTION: Serial data are converted into parallel data and temporarily stored in a FIFO memory 10. When the FIFO memory 10 is turned into full state, a control part 15 outputs a control signal for permitting the counting operation of a counter 17 and the counter 17 performs the counting of -1 from a preset value and designates the address of a RAM 13. Thus, the contents of the FIFO memory 10 are written in the RAM 13. When this write operation is completed, the control part 15 outputs a control signal for inhibiting the counting operation of the counter 17 and the counter 11 stops the counting operation and interrupts the address designation of the RAM 13. Since this operation is a hardware processing, even in the case of a large capacity data transmission, the burden on software processing can be reduced.</p> |
