| 摘要 |
PROBLEM TO BE SOLVED: To shorten a test time, and also easily prepare an evaluation program and an evaluation data by providing an interuption controller in a shared memory, and a slave processor and its memory in a local processor connecting bus. SOLUTION: A slave processor (MCPU) 40 reads response and memory test results stored in memories (RMEM) 32-36 of respective local processors (RCPU) 42-46, and transfers them by VEM transfer to a shared memory (SMEM) 16 to be stored. A data required for an operation of the MCPU 40 is stored in a memory 14 for the MCPU 40 to read a command generated in a host computor (EWS) 10 and written in the SMEM 16 to be fed to the respective RCPUs 42-46. The ESW 10 is facilitated thereby to divert data for the RCPUs 42-46 to the SMEM 16 in a lump, and status informations prepared in the respective RCPUs 42-46 are read thereby in a lump from the SMEM 16 by interuption signals from the plural MCPUs 40, so as to allow processing in a short time.
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