发明名称 INSULATED GATE BIPOLAR TRANSISTOR MODULE HAVING RESISTANCE TO SHORT-CIRCUITING
摘要 PROBLEM TO BE SOLVED: To prevent short-circuit of individual chips from causing damages to the entire module, by forming an eutectic mixed material of a layer which is joined to main electrodes of a silicon semiconductor and which contains silver and silicon. SOLUTION: Semiconductor chips 4 have main electrodes 5 and 6 which are coated with metal on both of tops and bottoms, and are electrically connected. The semiconductor chips 4 are supported on a conductive substrate 2, and connection pistons are arranged directly on every chips. A layer 7 arranged between the metal joining surfaces adjacent to either the main electrode 5 or the main electrode 6 is easily manufactured from a thin metal chip containing silver, or is applied to the main electrodes as paste. Usually, the thickness of the layer 7 is set to a half or larger than that of the semiconductor chip 4. Silver is suitable for the semiconductor 4 as a mating material of an eutectic material. The eutectic point of AgSi containing silver of 11% by the atomic weight is 835 deg.C, and this is far lower than the melting point of simple substance of silicon.
申请公布号 JP2000106374(A) 申请公布日期 2000.04.11
申请号 JP19990264189 申请日期 1999.09.17
申请人 ASEA BROWN BOVERI AG 发明人 LANG THOMAS DR;ZELLER HANS RUDOLF DR
分类号 H01L21/52;H01L23/051;H01L23/48;H01L23/488;H01L25/04;H01L25/07;(IPC1-7):H01L21/52 主分类号 H01L21/52
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