| 摘要 |
A method and circuit for self-latching data read lines that are used to transfer data that is read from a memory array of a memory device to a data output register of the memory device, wherein a self-latching latch circuit is connected to each data read line The latch circuits are located physically near the output of the memory array, for latching data that is read from the memory array as soon as the data is applied to the data read lines, and prior to the data being latched in the data output register, thereby minimizing the effects of propagation delay so that the memory cycle time can be decreased. In one embodiment wherein the memory is organized in a "x4" configuration, different groups of the data read lines are selected in alternate read cycles, and the data read lines of the non-selected data read group are equilibrated automatically during the read cycle using the conventional test circuits of the memory device.
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