| 摘要 |
Clock dejitter circuits are provided and comprise control circuits (30) for generating a plurality of pulses over a clock cycle, and clock circuits (60) for tracking the speeds of jittered incoming data signal arid based on those speeds, and utilizing the plurality of pulses, generating substantially unjittered data signals at the nominal rates of the jittered. incoming signals. A control circuit (30) broadly includes a divide by value x-divide by value x + I circuit (42) which receives a fast input clock signal, a modules y counter (46), and a count decode (52) for providing z control pulses over the count of y, and a logic gate (56) for taking the outputs from the count decode (52) and controlling the divide block (42) to guarantee that the divide block (42) divides the fast input clock signal by value x q.times for every r times the divide. block (42) divides the fast input clock signal by value x + i ; wherein q plus r equals y, and z equals either q+ I or r+ I.
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