| 摘要 |
PROBLEM TO BE SOLVED: To provide the PLL circuit with small power consumption, three- dimensional a short lock-up time and that can easily be large-scale-integrated and can be in operation even at a high frequency band. SOLUTION: The PLL circuit is provided with a variable frequency divider 11 that frequency-divides an output of a voltage controlled oscillator 12, a generating means 5 that generates a 1st reference signal and a 2nd reference signal whose phases differ from each other, a 1st comparator 6 that compares a phase of the 1st reference signal with a phase of an output of the variable frequency divider 11, a 2nd comparator 10 that compares a phase of the 2nd reference signal with a phase of the output of the variable frequency divider 11, a detector 17 that detects a lock state and a control section 18. |
