发明名称 |
System and method for maintaining memory coherency in a computer system having multiple system buses |
摘要 |
A cache-coherent, multiple-bus, multiprocessing system and method interconnects multiple system buses and an I/O bus to a shared main memory and efficiently maintains cache coherency while minimizing the impact to latency and total bandwidth within the system. The system provides coherency filters which coordinate bus-to-bus communications in such a way as to maintain cache memory coherency with a small amount of cross-bus traffic. In addition, the system provides a multiported pool of memory cells which interconnect the multiple buses.
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申请公布号 |
US6049847(A) |
申请公布日期 |
2000.04.11 |
申请号 |
US19990228717 |
申请日期 |
1999.01.12 |
申请人 |
COROLLARY, INC. |
发明人 |
VOGT, PETE D.;WHITE, GEORGE P.;CHANG, STEPHEN S. |
分类号 |
G06F12/08;G06F13/40;(IPC1-7):G06F13/14 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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