发明名称 Selective W CVD plug process with a RTA self-aligned W-silicide barrier layer
摘要 The present invention provides a method of fabricating a tungsten (W) plug 36 contact to a substrate using a selective W CVD Process with a self-aligned W-Silicide Barrier layer 34. The method comprises the steps of: forming first insulating layer 20 over a silicon semiconductor substrate 10; forming a first (contact) opening 24 in the first insulating layer 20 exposing the surface of the substrate; selectively growing a thin first tungsten layer 30 over the exposed substrate surface; rapidly thermally annealing the substrate forming a thin first tungsten silicide layer 34 from the thin first tungsten layer 30; selectively depositing a tungsten plug 36 over the first thin tungsten silicide layer 34 substantially filling the first opening 36 thereby forming a W plug contact. The RTA/W silicide layer 34 lowers the contact resistance, increases the adhesion and facilitates the selective deposition of the W plug 36.
申请公布号 US6048794(A) 申请公布日期 2000.04.11
申请号 US19970954048 申请日期 1997.10.20
申请人 INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE 发明人 CHEN, HSUEH-CHUNG;LOU, CHINE-GIE
分类号 H01L21/285;H01L21/768;(IPC1-7):H01L21/44 主分类号 H01L21/285
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