| 摘要 |
A method and system for a clock driver is described which can buffer an master clock directly, or generate a output clock signal having a balanced duty cycle which is the input clock frequency divided by a predetermined value. When a frequency control input, such as a rate signal, is switched, the clock output makes a glitchless transition from one frequency to the other. The clock driver includes a counter divider circuit with feedback to produce two signals related by a predetermined phase difference. The counter divider circuit employs predetermined logic delays by buffered gating controlled by the master clock, which produces two signals. These two signals act as "enable" control signals such that the timing of their rising and falling edges is arranged to never propagate through the clock divider circuit to become the edges of output clock. The master clock is gated with these two signals to provide two unbalanced signals which are synchronous to the input clock signal. In addition, these two unbalanced signals have waveforms such that they may then be logically combined to form a single, balanced signal in a glitchless manner. Furthermore, transitions between fast, slow, and disable modes of operation for such clock driver circuit are also synchronous with the master clock and glitchless.
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