发明名称 Data processor with multiple register queues
摘要 A data processor includes a register group having registers of the number larger than the number of registers which can be designated by a register specifier field of an instruction. The register group consists of a plurality of register queues with respect to logical register numbers designated in the instruction, each register queue including a plurality of physical registers. In the data processor, a physical register number forming section is provided for converting the logical register number to a physical register number in the register queue corresponding to the logical register number, by using queue control information designated in the register specifier field and read/write information decided by the kind of the instruction and the position of the register specifier field in the instruction.
申请公布号 US6049839(A) 申请公布日期 2000.04.11
申请号 US19930172170 申请日期 1993.12.23
申请人 HITACHI, LTD.;HITACHI ULSI ENGINEERING CORPORATION 发明人 FUJII, HIROAKI;INAGAMI, YASUHIRO;TAKEUCHI, SHIGEO
分类号 G06F9/34;G06F9/30;G06F9/38;(IPC1-7):G06F13/00 主分类号 G06F9/34
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