| 摘要 |
A computer system has first and second random access memory (RAM) modules for storing digital information, and first and second system controllers coupled to the first and second RAM modules, respectively. The first system controller has a first address decoder that allocates to the first RAM module a first set of addresses. The second system controller has a second address decoder that allocates to the second RAM module a second set of addresses. By employing two system controllers to control two RAM modules, a computer system can execute two memory transactions simultaneously and can eliminate or reduce the number of memory access delays incurred. The computer system can allocate addresses according to various interleaving schemes, such as page interleaving, cache line interleaving and word interleaving for different memory segments. A configuration register can be employed to allow programming to select which of the interleaving schemes to employ.
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