发明名称 PHASE-LOCKED LOOP CIRCUIT
摘要 PROBLEM TO BE SOLVED: To obtain the PLL circuit with low power consumption that realizes a high-speed lockup. SOLUTION: This phase-locked lop circuit has a phase difference conversion circuit consisting of a voltage controlled oscillator 108, a frequency divider 102 that frequency-divides an output of the voltage controlled oscillator 108, a reference frequency generator 101, a phase comparator 103 that compares a phase of an output of the reference frequency generator 101 with the phase of an output of the frequency divider 102, a charge pump 104 that converts a phase difference signal outputted from the phase comparator 103 into a control voltage of the voltage-controlled oscillator 108, and a low-pass filter 107. Furthermore, the phase-locked loop circuit also has a means that compares a phase difference obtained from an output of the phase comparator 103 with a reference value, to decide the quantity of the phase difference and a means that changes a power supply voltage applied to the phase comparator 103 and the charge pump 104, based on the decision result.
申请公布号 JP2000101429(A) 申请公布日期 2000.04.07
申请号 JP19980269550 申请日期 1998.09.24
申请人 发明人
分类号 H03L7/10;H03L7/08;H03L7/089;H03L7/18 主分类号 H03L7/10
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