发明名称 FERROELECTRIC MEMORY
摘要 PROBLEM TO BE SOLVED: To promote the decrease in voltage and power consumption by improving the reliability in a ferroelectric memory that is in a plate line drive system and has a dummy cell for preventing the compression of the amount of signal of a bit line, and a single-chip microcomputer or the like for mounting it. SOLUTION: A ferroelectric memory is provided with a memory cell array ARYR where a ferroelectric memory cell MC is arranged in a lattice as its basic component and is provided with a dummy cell DC for preventing the compression of the amount of signal of complementary bit lines DL1*-DLn* due to the coupling of ferroelectric capacitors Ct and Cb. In the ferroelectric memory, the other electrodes of ferroelectric capacitors Ct' and Cb' for composing the dummy cell DC are commonly coupled, and a dummy plate line DPL that is set to a low-level selection level essentially at the same timing as the specified bit of plate lines PL1-PLm for composing the memory cell array ARYR is returned to the high-level non-selection level immediately before a sense amplifier drive signal SASB is set to a low level and a unit sense amplifier UA of a sense amplifier SAR is set to an operation state.
申请公布号 JP2000100176(A) 申请公布日期 2000.04.07
申请号 JP19980272416 申请日期 1998.09.28
申请人 HITACHI LTD 发明人 TAKEUCHI MIKI;TANIGAWA HIROYUKI
分类号 G11C14/00;G11C11/22;H01L27/10;(IPC1-7):G11C14/00 主分类号 G11C14/00
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