CLOCK SYNCHRONIZATION CIRCUIT AND TRANSMITTER

摘要

PROBLEM TO BE SOLVED: To apply plural clock synchronization circuits to plural programs and to prevent an error accompanying the re-stamping of a PCR value. SOLUTION: A local clock 73 is prepared by frequency-dividing a source clock 71 inside this transmitter in an N/M frequency divider circuit 72, a PCR counter 74 is driven and an LMC value 75 is obtained. In order to increase the LMC value in synchronism with the PCR value included in the PCR packet of MPEG2 a frequency division cycle control circuit 77 adjusts a frequency division rate. The N/M frequency divider circuit 72 generates the pulses of the lock clock 73 for N pieces within a period capable of obtaining the M pieces of the pulses from the source clock 71. It is not required that the source clock 71 is a specified strict frequency. When this clock synchronization circuit is applied to the respective plural programs, the error of counting the time of passing through the device and re-stamping the PCR value of the PCR packet is not generated.