| 摘要 |
PROBLEM TO BE SOLVED: To provide a sampling clock reproducing circuit in simple constitution for being easily made into an IC and reducing jitters. SOLUTION: This circuit is constituted of a receiver 2 for receiving and demodulating signals modulated by data, a reference oscillator 10 for oscillating near the frequency of the integral multiple of the modulation speed of reception signals, a frequency division means 11 for frequency-dividing the output of the reference oscillator 10, a phase shift means 12 for shifting the phase of the output of the frequency division means 11 and outputting a reference clock, a phase comparator 3 for comparing the phases of the demodulation output of the receiver 2 and the reference clock of the phase shift means 12 and generating the output corresponding to a phase difference and an integration means 4 for integrating the output of the phase comparator 3 and controlling the ratio of phase shift in the phase shift means 12. The clock which is the double of the reference clock from the phase shift means 12 is turned to a sampling clock for data discrimination. |
