| 摘要 |
PROBLEM TO BE SOLVED: To reduce a circuit scale by providing a means for comparing an expectation value pattern and an output signal from a device under test(DUT) in a channel to be compared and separating and decoding into a total match detection signal and a total fail signal in a channel that is not to be compared. SOLUTION: The inside of a digital converter DC 70 is set to a fail signal generation means 90 only and the outside of the DC 70 is set to a logic OR means 82 only. In a channel to be compared, a fail signal generation means 90 outputs a fail signal FAILi that is obtained by comparing an expectation value paten EXPi being generated by a pattern generator PG with a corresponding signal output Di from a DUT. On the other hand, in a channel that is not to be compared, the output of the fail signal FAILi is prohibited. A logic OR means 82 receives fail signals FAIL1-FAILn of all channels and outputs a fail addition signal TFAIL, and a signal separation means 56 receives them and separates and decodes them into a total match detection signal and a total fail signal.
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