| 摘要 |
PROBLEM TO BE SOLVED: To provide a signal processing circuit capable of preventing dispersion in transmission timing of packets to be sent out to a serial interface bus. SOLUTION: A link core 120 of a link layer circuit 12 is used for transmitting/receiving signals containing control and data with a physical layer circuit 11 having peculiar control timing. A storage circuit 13 is provided for previously storing control timing data selected corresponding to the peculiar control timing of the physical layer circuit H connected to the link layer circuit 12. The link layer circuit 12 is provided with an auto load circuit 130 and a register 129 for setting the control timing data stored in the storage circuit 13 so as to be used for exchanging the signals containing the control and data between the link core 120 and physical layer circuit 11 through the auto load circuit 130.
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