| 摘要 |
PROBLEM TO BE SOLVED: To provide a method of designing a gate array integrated circuit whereby the chip size is suppressed from increasing. SOLUTION: Core unit cells 11, 21 for forming internal logic circuits of the gate array integrated circuit are composed of transistors, etc., and laid like a matrix in inner block regions 10 defined by a central part of a chip and in input/output circuit-priority inner regions 20 defined outside the inner block regions 10, input circuits and output circuits pre-drivers of the gate array integrated circuit are disposed in the input/output circuit-priority inner regions 20 and those inner logic circuits not held in the inner block regions 10 are formed in unused portions of the input/output circuit-priority inner regions 20.
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