| 摘要 |
PROBLEM TO BE SOLVED: To prevent the drop of an access speed when a write access follows a read access in the access of a high speed CPU to a low speed device and to prevent data collision between both the accesses. SOLUTION: An inverted output of a NAND gate 12 while the periods of H levels of a read access signal RD and a write access signal WT are overlapped sets a JK flip-flop (JK-FF) 14. When a counter 15 is reset by a signal RW*, it counts the number of clocks of a clock CLK. A memory management unit 11 extracts delay value (the number of clocks) corresponding to the address of data to be written with the next write access from registers IDL1 to IDLn. When the delay value coincides with count value, a comparator 16 resets the JK-FF 14. An inverted output of the JK-FF 14 delays an access control signal NXTACS instructing the next access in an AND gate 17.
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