DEVICE AND METHOD FOR SYNCHRONIZATION, AND INTERFACE CIRCUIT

摘要

PROBLEM TO BE SOLVED: To make eliminable the need for double buffering for all asynchronous data signals crossing a border by generating output pulses of a 2nd clock domain in response to a transition generated in the output of a 1st clock domain. SOLUTION: The input to a 1st flip-flop(FF) 32 represents the least significant bit(LSB) of a counter 31 included in the 1st clock domain and a CLK signal is generated from the 2nd clock domain. The output of the 1st FF 32 is supplied to a 2nd FF 34, whose output is supplied to a 3rd FF 35 and an exclusive OR (XOR) gate 38. In response to the outputs from the 2nd and 3rd FFs 34 and 36, the XOR gate 38 generates a synchronizing signal generated in the 2nd clock domain. Thus, one asynchronous input signal, i.e., LSB input is usable to synchronize a large number of data inputs. This results in that double buffering is unnecessary for all asynchronous data inputs.